1. Field of the Invention
The present invention relates to techniques as to generation of zigzag addresses for DCT (discrete cosine transformation) which is employed for band compression of image data.
2. Description of the Background Art
FIG. 59 is a block diagram showing a conventional zigzag address generation circuit. An output of a counter 7 which receives clock and reset signals is inputted to a storage element 6. The storage element 6 is formed by a ROM, for example, to store zigzag addresses in a prescribed order. The output of the counter 7 is first zeroed by the reset signal, and thereafter successively incremented as 1, 2, 3 in synchronization with the clock signal. On the other hand, the storage element 6 successively outputs its storage contents with addresses of the outputs of the counter 7. When the zigzag addresses are stored in the prescribed order as described later, therefore, the storage element 6 successively generates the zigzag addresses.
FIG. 60 shows another zigzag address generation circuit, which is disclosed in Japanese Patent Laying-Open Gazette No. 3-63883 (1991). A control part 5 monitors an underflow signal and a match detection signal to control updown counters 1 and 2 for generating X and Y address outputs respectively. These address outputs form the zigzag addresses.
Namely, the updown counters 1 and 2 are reset in initial states so that both X and Y addresses are zeroed. One of the counters 1 and 2 is driven as an up counter while the other one is driven as a down counter. When one of the counters generates an underflow signal, the counting operations are temporarily stopped and the counters are again driven as up counters. This also applies to such case that a match detection signal is outputted from either one of comparators 3 and 4. Such operations are controlled by the control part 5.
Since the conventional zigzag address generation circuits are formed in the aforementioned manners, the storage element 6 must have sufficiently large storage capacity with respect to the addresses to be generated in the circuit shown in FIG. 59, while operations for controlling the counters 1 and 2 and the comparators 3 and 4 are complicated in the circuit shown in FIG. 60.